1. Field of the Invention
The present invention relates to a memory device that protects data or reduces data errors by using an index such as a failure occurrence risk.
2. Description of the Related Art
A flash memory is beginning to be used as a memory device as the nonvolatile semiconductor memory techniques advance. The insulation properties of a thin insulating film of a memory device deteriorates with time because the film is exposed to a severe voltage load and temperature change when writing or erasing data. A high electric field applied to an oxide during erase and programming changes the structure of the insulating film, and produces an electron trap failure in the oxide layer. The structural failure causes a leak of electric charge in a floating gate. A number of failures occur with time, and the oxide layer finally breaks. If the deterioration of the insulation properties of a tunnel oxide exceeds a threshold value, no data can be erased from or programmed in a memory cell. Therefore, to prolong the life limited by the deterioration of the insulation properties of a flash memory, a data management strategy called wear leveling is performed. A wear leveling algorithm evenly disperses an erase/program cycle in all data storage areas (memory cells/blocks/pages/planes). Wear leveling is adopted as a technique that prolongs the fault life caused by the deterioration of the insulation properties of a device (semiconductor memory) by thus dispersing the erase/program cycle in the entire device, thereby preventing a data hot spot (see, e.g., JP-A No. 2008-139927 (KOKAI)).
In a memory device such as a solid state drive (SSD) in which a plurality of semiconductor memory devices are mounted on a circuit board, however, not only the deterioration of a memory in a user's use log but also a fatigue crack in a solder joint location connecting the memory and board or in a substrate interconnection is also a main failure mode.
On the other hand, the electronic device health monitoring technique can calculate, either periodically or in real time, the failure occurrence probability or the remaining life with respect to a fatigue crack in a solder joint location or interconnection on a semiconductor packaging substrate, from a data aggregate obtainable from a sensor or monitoring tool embedded in an electronic device (see, e.g., JP-A No. 2008-241432 (KOKAI)).
A memory device such as a solid state drive (SSD) including a plurality of semiconductor memories (e.g., flash memories) is required to have high data write/read reliability, high power-saving properties, and a high speed. To achieve these requirements, a mechanism for protecting data and a mechanism for reducing data errors are necessary. Means for solving the problem of the deterioration of the insulation properties of a semiconductor memory and the problem of the interference between close memory pages already exist. However, the deterioration of the insulation properties and the interference between adjacent memory pages are not the only causes of data corruption in a memory device using a semiconductor memory such as a flash memory. For example, a plurality of flash memory packages and a control IC in a solid state drive are connected to a printed circuit board via a large number of solder joint locations, and these solder joint locations or interconnections may cause a fatigue crack owing to a temperature cycle or mechanical load.